The present invention relates generally to bipolar devices, and more particularly to bipolar devices compatible with CMOS process technology, and implemented in a mesh structure to enhance the performance.
Although CMOS devices have advantages of low power consumption and high input impedance, they often need some specially designed I/O devices and circuits to protect them from high voltage signals. Those I/O devices and circuits usually require extra masks in the course of semiconductor processing. One way to simplify the semiconductor processing is to use bipolar devices as the I/O devices. The bipolar devices are able to sustain high voltages, easy to manufacture, and fully compatible with conventional CMOS process technologies. In addition, bipolar devices have many advantages over CMOS devices in designing analog circuitry. For example, bipolar devices can offer a higher current gain, lower noise, a higher driving capability, and less device mismatch than MOS devices for the same current. It would be desirable to use bipolar devices together with CMOS devices in certain circuits to achieve better and balanced performance for circuitries.
FIG. 1 illustrates a conventional PNP bipolar transistor 10 compatible with CMOS process technologies. The LOCal Oxidation of Silicon (LOCOS) isolations 11 define three active areas 12, 13 and 14 on N well 15 in a semiconductor substrate. The active areas 12 and 13 doped with P-type impurities form an emitter 16 and collector 17, respectively. The LOCOS isolation 11 between the emitter 16 and collector 17 defines an intrinsic base 18 thereunder in the N well 15. An extrinsic base 19 is electrically connected to the intrinsic base 18 via the body of the N well 15. The extrinsic base 19 is doped with N type of impurities to improve its conductivity. When the emitter 16, collector 17 and extrinsic base 19 are properly biased, carriers would flow between the emitter 16 and the collector 17 to produce amplification of currents. Such bipolar transistor can be found in U.S. Patent Application Publication No. US 2006/0197185.
The performance of the PNP bipolar transistor 10 greatly depends on the width of the intrinsic base 18 and its distance to the extrinsic base 19. Conventionally, its current gain β, about 1-5, is too small to satisfy many circuit designs. Furthermore, if a Shallow Trench Isolations (STI) instead of a LOCOS isolation is used, it is almost impossible for carriers to travel between the collector and emitter over the STI. This further degrades the bipolar transistor's performance.
FIG. 2 illustrates a layout view of a conventional bipolar device 20 proposed to address the above issues. The bipolar device 20 is constructed on an N well 22, which is implemented on a semiconductor substrate (not shown in the figure). An isolation region 24, such as LOCOS or shallow trench isolation, is formed on the N well 22 to define an active area 26. A conductive gate 28 is formed across the active area 26. P+ doped regions 30a and 30b are formed adjacent to the conductive gate 28 on the N well 22 within the isolation region 24. N+ doped regions 32a and 32b with dosage higher than that of the N well 32 are implemented partially overlapping the N well 22 underneath the conductive gate 28 at the two longitudinal ends thereof. Extrinsic base contacts 34a and 34b are constructed on the N+ doped regions 32a and 32b, respectively, and together with the N well 22 underneath the conductive gate 28 forming the base of the bipolar device 20.
In operation, one of the P+ doped regions 30a and 30b functions as an emitter and the other as a collector. The base of the bipolar device 20 is comprised of the intrinsic base, the portion of the N well 22 underneath the conductive gate 28, and the extrinsic base including both the N+ dope regions 32a and 32b. Since the N+ doped regions 32a and 32b are placed at two longitudinal ends of the conductive gate 28, the distance between the intrinsic base and the extrinsic base is shortened, and the resistance there between is reduced as opposed to that of the prior art as shown in FIG. 1. As a result, the bipolar device 20 can achieve a higher current gain, compared to about 1 to 5 produced by the conventional bipolar device shown in FIG. 1.
FIG. 3 illustrates a conventional layout view of a bipolar device array 40 disclosed in the U.S. Patent Application Publication No. US 2007/0105301. The bipolar device array 40 is constructed on an N well 44, which is implemented on a semiconductor substrate (not shown in the figure). Rows and columns of conductive gates 42a and 42b are constructed on the N well 44. The conductive gates 42a and 42b are formed together with the gates of MOS transistor on the semiconductor substrate. The conductive gates 42a include a set of parallel lines crossing another set of parallel lines designated by 42b. P+ doped regions 46 are implemented on the N well 44 in areas between the conductive gates 42a and 42b, except for the N+ doped regions 48 designated by the broken lines. The N well 44 underneath the conductive gates 42a and 42b has an N-type polarity, without being affected during the formation of the P+ doped regions 46, as the conductive gates 42a and 42b shield off the P-type ions during the ion implantation process when forming the P+ doped regions 46. Contacts 49 are constructed on the P+ doped regions 46 and the N+ doped regions 48.
Every two adjacent P+ doped regions 46 function as a collector and an emitter, respectively. The N well 44 underneath the conductive gates 42a and 42b functions as intrinsic bases, whereas the N+ doped regions 48 function as extrinsic bases. Each emitter and its surrounding collectors and bases function together as a PNP bipolar device, and rows and columns of such bipolar devices make up the bipolar device array 40. The bipolar device array 40 has the advantages of reduced base resistance and increased device layout density.
In view of the foregoing, there is still room for improvement on the architecture and the layout of the conventional bipolar devices in order to increase the current gain and the device layout density.